p1 Limits of Bias Based Assist Methods in Nano-Scale 6T SRAM

1. Introduction
Increased device variability and reduced overdrive associated with lower operating voltages have reduced the functional yield margins in VLSI circuits.

Because of the commercial success of the 6T SRAM, methods to address the failure mechanisms of large memory arrays will extend the life of the 6T SRAM in VLSI circuits

(page 1, col 2)
The objective of this paper is to explore the boundaries of bias based assist methods to understand the impact on the minimum operation voltage (Vmin) and the effectiveness of the assist methods for future generations of 6T SRAM

2. Bias based assist methods
Read assist methods refer to the set of circuit options that
are used to either reduce the read noise source or improve the
cell stability so that the cell remains stable during a read
access.

3. Quantifying assist limits
Figure 1 shows the read static noise margin (SNM)
response to modulated voltage bias across the four
technology nodes (65nm-22nm) considered in this work

(page 3)
We will use a margin/delay analysis to compare the assist
methods.

Using the 45nm LP-PTM technology, we illustrate the
margin/delay concept for write and read in Figure 3(a) and
(b), respectively.

(page 3 col 2)

We characterize this margin/delay relationship
schematically in Figure 4 to capture the response for both
read and write assist.

The functional window boundaries, shown schematically
in Figure 4, are established by four factors, (1) array size, (2)
variation, (3) the delay requirement, and the (4) target soft
fail yield requirement for the array

(page 4)

By application of the constraint limitations we may then
begin to map the maximum assist margin values permissible

In addition to the technology defined Vmax constraint,
other assist bias constraints for read assist bias include;
forward bias diode turn-on (Vfwd) when VSSc is
intentionally driven below ground, and cell upset by writing a
zero when both bit lines are drooped sufficiently low (Write
0).

(page 4 col 2)

4. Results
To examine the maximum soft fail limited yield
boundaries that can be achieved for a given assist method, we
will first describe the relationship with VDD and then apply
the assist bias using the Vmax constraint.

Competing mechanisms produce a different result with
negative VSSc.

While the cell stability compensation is larger for VDDc
assist, the improvement in performance (read delay) may not
be sufficient depending on the functional window as
discussed earlier.

We next examine the margin/delay relationship for the
assist methods with maximum assist bias.

(p5)
For the cases we studied, the read ALC as defined by the
latch supply voltages were found to provide a reasonable
approximation of the full multi-terminal Vmax read assist
contour.